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Features
* High Performance, Low Power AVR(R) 8-Bit Microcontroller * Advanced RISC Architecture
- 130 Powerful Instructions - Most Single Clock Cycle Execution - 32 x 8 General Purpose Working Registers - Fully Static Operation - Up to 16 MIPS Throughput at 16 MHz - On-Chip 2-cycle Multiplier High Endurance Non-volatile Memory Segments - In-System Self-programmable Flash Program Memory * 32K Bytes (ATmega325/ATmega3250) * 64K Bytes (ATmega645/ATmega6450) - EEPROM * 1K bytes (ATmega325/ATmega3250) * 2K bytes (ATmega645/ATmega6450) - Internal SRAM * 2K bytes (ATmega325/ATmega3250) * 4K bytes (ATmega645/ATmega6450) - Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM - Data retention: 20 years at 85C/100 years at 25C(1) - Optional Boot Code Section with Independent Lock Bits * In-System Programming by On-chip Boot Program * True Read-While-Write Operation - Programming Lock for Software Security JTAG (IEEE std. 1149.1 compliant) Interface - Boundary-scan Capabilities According to the JTAG Standard - Extensive On-chip Debug Support - Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface Peripheral Features - Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode - One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode - Real Time Counter with Separate Oscillator - Four PWM Channels - 8-channel, 10-bit ADC - Programmable Serial USART - Master/Slave SPI Serial Interface - Universal Serial Interface with Start Condition Detector - Programmable Watchdog Timer with Separate On-chip Oscillator - On-chip Analog Comparator - Interrupt and Wake-up on Pin Change Special Microcontroller Features - Power-on Reset and Programmable Brown-out Detection - Internal Calibrated Oscillator - External and Internal Interrupt Sources - Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and Standby I/O and Packages - 53/68 Programmable I/O Lines - 64-lead TQFP, 64-pad QFN/MLF, and 100-lead TQFP Speed Grade: - ATmega325V/ATmega3250V/ATmega645V/ATmega6450V: * 0 - 4 MHz @ 1.8 - 5.5V, 0 - 8 MHz @ 2.7 - 5.5V - ATmega325/3250/645/6450: * 0 - 8 MHz @ 2.7 - 5.5V, 0 - 16 MHz @ 4.5 - 5.5V Temperature range: - -40C to 85C Industrial Ultra-Low Power Consumption - Active Mode: 1 MHz, 1.8V: 350 A 32 kHz, 1.8V: 20 A (including Oscillator) - Power-down Mode: 100 nA at 1.8V
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8-bit Microcontroller with In-System Programmable Flash ATmega325/V ATmega3250/V ATmega645/V ATmega6450/V Preliminary Summary
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1. Pin Configurations
Figure 1-1. Pinout ATmega3250/6450
PF5 (ADC5/TMS) PF6 (ADC6/TDO) PF4 (ADC4/TCK) PF7 (ADC7/TDI) PH7 (PCINT23) PH6 (PCINT22) PH5 (PCINT21) PH4 (PCINT20) PF0 (ADC0) PF2 (ADC2) PF3 (ADC3) PF1(ADC1)
AGND
AVCC
AREF
GND
DNC
DNC
DNC
DNC
DNC
VCC
PA0
PA1 77
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
DNC (RXD/PCINT0) PE0 (TXD/PCINT1) PE1 (XCK/AIN0/PCINT2) PE2 (AIN1/PCINT3) PE3 (USCK/SCL/PCINT4) PE4 (DI/SDA/PCINT5) PE5 (DO/PCINT6) PE6 (CLKO/PCINT7) PE7 VCC GND DNC (PCINT24) PJ0 (PCINT25) PJ1 DNC DNC DNC DNC (SS/PCINT8) PB0 (SCK/PCINT9) PB1 (MOSI/PCINT10) PB2 (MISO/PCINT11) PB3 (OC0A/PCINT12) PB4 (OC1A/PCINT13) PB5 (OC1B/PCINT14) PB6
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
76
PA2
75 74 INDEX CORNER 73 72 71 70 69 68 67 66 65 64
PA3 PA4 PA5 PA6 PA7 PG2 PC7 PC6 DNC PH3 (PCINT19) PH2 (PCINT18) PH1 (PCINT17) PH0 (PCINT16) DNC DNC DNC DNC PC5 PC4 PC3 PC2 PC1 PC0 PG1 PG0
ATmega3250/6450
63 62 61 60 59 58 57 56 55 54 53 52 51
(T1) PG3
(T0) PG4
(PCINT26) PJ2
(PCINT27) PJ3
(PCINT28) PJ4
(PCINT29) PJ5
(PCINT30) PJ6
(ICP1) PD0
(OC2A/PCINT15) PB7
RESET/PG5
(INT0) PD1
DNC
VCC
GND
DNC
DNC
DNC
PD2
PD3
PD4
PD5
PD6
XTAL2 (TOSC2)
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ATmega325/3250/645/6450
2570LS-AVR-08/07
XTAL1 (TOSC1)
PD7
ATmega325/3250/645/6450
Figure 1-2. Pinout ATmega325/645
PF5 (ADC5/TMS) PF6 (ADC6/TDO) PF4 (ADC4/TCK) PF7 (ADC7/TDI) PF0 (ADC0) PF1 (ADC1) PF2 (ADC2) PF3 (ADC3)
AVCC
AREF
GND
GND
VCC
PA1 50
PA0
61
60
59
58
57
56
55
54
53
52
51
64
63
DNC (RXD/PCINT0) PE0 (TXD/PCINT1) PE1 (XCK/AIN0/PCINT2) PE2 (AIN1/PCINT3) PE3 (USCK/SCL/PCINT4) PE4 (DI/SDA/PCINT5) PE5 (DO/PCINT6) PE6 (CLKO/PCINT7) PE7 (SS/PCINT8) PB0 (SCK/PCINT9) PB1 (MOSI/PCINT10) PB2 (MISO/PCINT11) PB3 (OC0A/PCINT12) PB4 (OC1A/PCINT13) PB5 (OC1B/PCINT14) PB6
62
49
48 PA3 47 PA4 46 PA5 45 PA6 44 PA7 43 PG2 42 PC7 41 PC6 40 PC5 39 PC4 38 PC3 37 PC2 36 PC1 35 PC0 34 PG1 33 PG0
1 2 INDEX CORNER 3 4 5 6 7 8 9 10 11 12 13 14 15 16
ATmega325/645
GND 22
XTAL2 (TOSC2) 23
XTAL1 (TOSC1) 24
(ICP1) PD0 25
PD1 (INT0) 26
PD2 27
PD3 28
(OC2A/PCINT15) PB7 17
(T1) PG3 18
(T0) PG4 19
RESET/PG5 20
VCC 21
PD4 29
PD5 30
PD6 31
Note:
The large center pad underneath the QFN/MLF packages is made of metal and internally connected to GND. It should be soldered or glued to the board to ensure good mechanical stability. If the center pad is left unconnected, the package might loosen from the board.
2. Disclaimer
Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized.
3. Overview
The ATmega325/3250/645/6450 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega325/3250/645/6450 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.
PD7 32
PA2
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2570LS-AVR-08/07
3.1
Block Diagram
Block Diagram
Figure 3-1.
GND
VCC
PF0 - PF7
PA0 - PA7
PC0 - PC7
PORTF DRIVERS
PORTA DRIVERS
PORTC DRIVERS
DATA REGISTER PORTF
DATA DIR. REG. PORTF
DATA REGISTER PORTA
DATA DIR. REG. PORTA
DATA REGISTER PORTC
DATA DIR. REG. PORTC
8-BIT DATA BUS
AVCC AGND AREF ADC CALIB. OSC INTERNAL OSCILLATOR OSCILLATOR JTAG TAP PROGRAM COUNTER STACK POINTER WATCHDOG TIMER
DATA DIR. REG. PORTH
TIMING AND CONTROL
PORTH DRIVERS
ON-CHIP DEBUG
PROGRAM FLASH
SRAM
MCU CONTROL REGISTER
PH0 - PH7
DATA REGISTER PORTH
BOUNDARYSCAN
INSTRUCTION REGISTER
GENERAL PURPOSE REGISTERS
X Y Z
TIMER/ COUNTERS
PROGRAMMING LOGIC
INSTRUCTION DECODER
INTERRUPT UNIT
XTAL1
XTAL2
DATA DIR. REG. PORTJ
CONTROL LINES
ALU
EEPROM
PORTJ DRIVERS
AVR CPU
STATUS REGISTER
PJ0 - PJ6
DATA REGISTER PORTJ
USART
UNIVERSAL SERIAL INTERFACE
SPI
ANALOG COMPARATOR
DATA REGISTER PORTE
DATA DIR. REG. PORTE
DATA REGISTER PORTB
DATA DIR. REG. PORTB
DATA REGISTER PORTD
DATA DIR. REG. PORTD
DATA REG. PORTG
DATA DIR. REG. PORTG
+ -
PORTE DRIVERS
PORTB DRIVERS
PORTD DRIVERS
PORTG DRIVERS
PE0 - PE7
PB0 - PB7
PD0 - PD7
PG0 - PG4
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
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ATmega325/3250/645/6450
2570LS-AVR-08/07
RESET
ATmega325/3250/645/6450
The ATmega325/3250/645/6450 provides the following features: 32/64K bytes of In-System Programmable Flash with Read-While-Write capabilities, 1/2K bytes EEPROM, 2/4K byte SRAM, 54/69 general purpose I/O lines, 32 general purpose working registers, a JTAG interface for Boundary-scan, On-chip Debugging support and programming, three flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, Universal Serial Interface with Start Condition Detector, an 8-channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, an SPI serial port, and five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Power-save mode, the asynchronous timer will continue to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with lowpower consumption. The device is manufactured using Atmel's high density non-volatile memory technology. The On-chip In-System re-Programmable (ISP) Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot program running on the AVR core. The Boot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega325/3250/645/6450 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega325/3250/645/6450 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits.
3.2
Comparison between ATmega325, ATmega3250, ATmega645 and ATmega6450
The ATmega325, ATmega3250, ATmega645, and ATmega6450 differs only in memory sizes, pin count and pinout. Table 3-1 on page 5 summarizes the different configurations for the four devices. Table 3-1.
Device ATmega325 ATmega3250 ATmega645 ATmega6450
Configuration Summary
Flash 32K bytes 32K bytes 64K bytes 64K bytes EEPROM 1K bytes 1K bytes 2K bytes 2K bytes RAM 2K bytes 2K bytes 4K bytes 4K bytes General Purpose I/O Pins 54 69 54 69
3.3
Pin Descriptions
The following section describes the I/O-pin special functions.
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2570LS-AVR-08/07
3.3.1
VCC Digital supply voltage.
3.3.2
GND Ground.
3.3.3
Port A (PA7..PA0) Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B has better driving capabilities than the other ports. Port B also serves the functions of various special features of the ATmega325/3250/645/6450 as listed on page 67.
3.3.4
3.3.5
Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega325/3250/645/6450 as listed on page 70.
3.3.6
3.3.7
Port E (PE7..PE0) Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the ATmega325/3250/645/6450 as listed on page 71.
6
ATmega325/3250/645/6450
2570LS-AVR-08/07
ATmega325/3250/645/6450
3.3.8 Port F (PF7..PF0) Port F serves as the analog inputs to the A/D Converter. Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset occurs. Port F also serves the functions of the JTAG interface. 3.3.9 Port G (PG5..PG0) Port G is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port G output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up resistors are activated. The Port G pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port G also serves the functions of various special features of the ATmega325/3250/645/6450 as listed on page 71. 3.3.10 Port H (PH7..PH0) Port H is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port H output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port H pins that are externally pulled low will source current if the pull-up resistors are activated. The Port H pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port H also serves the functions of various special features of the ATmega3250/6450 as listed on page 71. 3.3.11 Port J (PJ6..PJ0) Port J is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port J output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port J pins that are externally pulled low will source current if the pull-up resistors are activated. The Port J pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port J also serves the functions of various special features of the ATmega3250/6450 as listed on page 71. 3.3.12 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 28-4 on page 300. Shorter pulses are not guaranteed to generate a reset. 3.3.13 XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
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2570LS-AVR-08/07
3.3.14
XTAL2 Output from the inverting Oscillator amplifier.
3.3.15
AVCC AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter.
3.3.16
AREF This is the analog reference pin for the A/D Converter.
4. Resources
A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr.
Note: 1.
5. Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85C or 100 years at 25C.
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ATmega325/3250/645/6450
2570LS-AVR-08/07
ATmega325/3250/645/6450
6. Register Summary
Note:
Address
(0xFF) (0xFE) (0xFD) (0xFC) (0xFB) (0xFA) (0xF9) (0xF8) (0xF7) (0xF6) (0xF5) (0xF4) (0xF3) (0xF2) (0xF1) (0xF0) (0xEF) (0xEE) (0xED) (0xEC) (0xEB) (0xEA) (0xE9) (0xE8) (0xE7) (0xE6) (0xE5) (0xE4) (0xE3) (0xE2) (0xE1) (0xE0) (0xDF) (0xDE) (0xDD) (0xDC) (0xDB) (0xDA) (0xD9) (0xD8) (0xD7) (0xD6) (0xD5) (0xD4) (0xD3) (0xD2) (0xD1) (0xD0) (0xCF) (0xCE) (0xCD) (0xCC) (0xCB) (0xCA) (0xC9) (0xC8) (0xC7) (0xC6) (0xC5) (0xC4)
Registers with bold type only available in ATmega3250/6450.
Bit 6
PORTJ6 DDJ6 PINJ6 PORTH6 DDH6 PINH6 -
Name
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PORTJ DDRJ PINJ PORTH DDRH PINH Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved UDR0 UBRR0H UBRR0L
Bit 7
PORTH7 DDH7 PINH7 -
Bit 5
PORTJ5 DDJ5 PINJ5 PORTH5 DDH5 PINH5 -
Bit 4
PORTJ4 DDJ4 PINJ4 PORTH4 DDH4 PINH4 -
Bit 3
PORTJ3 DDJ3 PINJ3 PORTH3 DDH3 PINH3 -
Bit 2
PORTJ2 DDJ2 PINJ2 PORTH2 DDH2 PINH2 -
Bit 1
PORTJ1 DDJ1 PINJ1 PORTH1 DDH1 PINH1 -
Bit 0
PORTJ0 DDJ0 PINJ0 PORTH0 DDH0 PINH0 -
Page
83 83 83 83 83 83
USART0 Data Register USART0 Baud Rate Register High USART0 Baud Rate Register Low
178 183 183
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2570LS-AVR-08/07
Address
(0xC3) (0xC2) (0xC1) (0xC0) (0xBF) (0xBE) (0xBD) (0xBC) (0xBB) (0xBA) (0xB9) (0xB8) (0xB7) (0xB6) (0xB5) (0xB4) (0xB3) (0xB2) (0xB1) (0xB0) (0xAF) (0xAE) (0xAD) (0xAC) (0xAB) (0xAA) (0xA9) (0xA8) (0xA7) (0xA6) (0xA5) (0xA4) (0xA3) (0xA2) (0xA1) (0xA0) (0x9F) (0x9E) (0x9D) (0x9C) (0x9B) (0x9A) (0x99) (0x98) (0x97) (0x96) (0x95) (0x94) (0x93) (0x92) (0x91) (0x90) (0x8F) (0x8E) (0x8D) (0x8C) (0x8B) (0x8A) (0x89) (0x88) (0x87) (0x86) (0x85)
Name
Reserved UCSR0C UCSR0B UCSR0A Reserved Reserved Reserved Reserved Reserved USIDR USISR USICR Reserved ASSR Reserved Reserved OCR2A TCNT2 Reserved TCCR2A Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved OCR1BH OCR1BL OCR1AH OCR1AL ICR1H ICR1L TCNT1H
Bit 7
RXCIE0 RXC0 USISIF USISIE -
Bit 6
UMSEL0 TXCIE0 TXC0 USIOIF USIOIE -
Bit 5
UPM01 UDRIE0 UDRE0 USIPF USIWM1 -
Bit 4
UPM00 RXEN0 FE0 USIDC USIWM0 EXCLK -
Bit 3
USBS0 TXEN0 DOR0 USICNT3 USICS1 AS2 -
Bit 2
UCSZ01 UCSZ02 UPE0 USICNT2 USICS0 TCN2UB -
Bit 1
UCSZ00 RXB80 U2X0 USICNT1 USICLK OCR2UB -
Bit 0
UCPOL0 TXB80 MPCM0 -
Page
181 180 179
USI Data Register USICNT0 USITC TCR2UB -
191 192 193 144
Timer/Counter 2 Output Compare Register A Timer/Counter2 FOC2A WGM20 COM2A1 COM2A0 WGM21 CS22 CS21 CS20 -
144 144 142
Timer/Counter1 Output Compare Register B High Timer/Counter1 Output Compare Register B Low Timer/Counter1 Output Compare Register A High Timer/Counter1 Output Compare Register A Low Timer/Counter1 Input Capture Register High Timer/Counter1 Input Capture Register Low Timer/Counter1 High
126 126 126 126 126 126 126
10
ATmega325/3250/645/6450
2570LS-AVR-08/07
ATmega325/3250/645/6450
Address
(0x84) (0x83) (0x82) (0x81) (0x80) (0x7F) (0x7E) (0x7D) (0x7C) (0x7B) (0x7A) (0x79) (0x78) (0x77) (0x76) (0x75) (0x74) (0x73) (0x72) (0x71) (0x70) (0x6F) (0x6E) (0x6D) (0x6C) (0x6B) (0x6A) (0x69) (0x68) (0x67) (0x66) (0x65) (0x64) (0x63) (0x62) (0x61) (0x60) 0x3F (0x5F) 0x3E (0x5E) 0x3D (0x5D) 0x3C (0x5C) 0x3B (0x5B) 0x3A (0x5A) 0x39 (0x59) 0x38 (0x58) 0x37 (0x57) 0x36 (0x56) 0x35 (0x55) 0x34 (0x54) 0x33 (0x53) 0x32 (0x52) 0x31 (0x51) 0x30 (0x50) 0x2F (0x4F) 0x2E (0x4E) 0x2D (0x4D) 0x2C (0x4C) 0x2B (0x4B) 0x2A (0x4A) 0x29 (0x49) 0x28 (0x48) 0x27 (0x47) 0x26 (0x46)
Name
TCNT1L Reserved TCCR1C TCCR1B TCCR1A DIDR1 DIDR0 Reserved ADMUX ADCSRB ADCSRA ADCH ADCL Reserved Reserved Reserved Reserved PCMSK3 Reserved Reserved TIMSK2 TIMSK1 TIMSK0 PCMSK2 PCMSK1 PCMSK0 Reserved EICRA Reserved Reserved OSCCAL Reserved PRR Reserved Reserved CLKPR WDTCR SREG SPH SPL Reserved Reserved Reserved Reserved Reserved SPMCSR Reserved MCUCR MCUSR SMCR Reserved OCDR ACSR Reserved SPDR SPSR SPCR GPIOR2 GPIOR1 Reserved Reserved OCR0A TCNT0
Bit 7
FOC1A ICNC1 COM1A1 ADC7D REFS1 ADEN
Bit 6
FOC1B ICES1 COM1A0 ADC6D REFS0 ACME ADSC
Bit 5
COM1B1 ADC5D ADLAR ADATE
Bit 4
WGM13 COM1B0 ADC4D MUX4 ADIF
Bit 3
WGM12 ADC3D MUX3 ADIE
Bit 2
CS12 ADC2D MUX2 ADTS2 ADPS2
Bit 1
CS11 WGM11 AIN1D ADC1D MUX1 ADTS1 ADPS1
Bit 0
CS10 WGM10 AIN0D ADC0D MUX0 ADTS0 ADPS0
Page
126 125 124 122 199 216 212 197/216 214 215 215
Timer/Counter1 Low
ADC Data Register High ADC Data Register Low PCINT23 PCINT15 PCINT7 CLKPCE I PCINT30 PCINT22 PCINT14 PCINT6 T PCINT29 ICIE1 PCINT21 PCINT13 PCINT5 H PCINT28 PCINT20 PCINT12 PCINT4 WDCE S PCINT27 PCINT19 PCINT11 PCINT3 PRTIM1 CLKPS3 WDE V PCINT26 OCIE1B PCINT18 PCINT10 PCINT2 PRSPI CLKPS2 WDP2 N PCINT25 OCIE2A OCIE1A OCIE0A PCINT17 PCINT9 PCINT1 ISC01 PSUSART0 CLKPS1 WDP1 Z PCINT24 TOIE2 TOIE1 TOIE0 PCINT16 PCINT8 PCINT0 ISC00 -
57
145 127 98 57 58 58 55
Oscillator Calibration Register [CAL7..0] PRADC CLKPS0 WDP0 C
31 39
31 46 11 13 13
Stack Pointer High Stack Pointer Low SPMIE JTD IDRD/OCDR7 ACD SPIF SPIE RWWSB OCDR6 ACBG WCOL SPE OCDR5 ACO DORD RWWSRE PUD JTRF OCDR4 ACI MSTR BLBSET WDRF SM2 OCDR3 ACIE CPOL PGWRT BORF SM1 OCDR2 ACIC CPHA PGERS IVSEL EXTRF SM0 OCDR1 ACIS1 SPR1 SPMEN IVCE PORF SE OCDR0 ACIS0 -
262 52/80/226 46 34 222 197 155
SPI Data Register SPI2X SPR0
155 153 24 24
General Purpose I/O Register General Purpose I/O Register Timer/Counter0 -
Timer/Counter0 Output Compare A
97 97
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2570LS-AVR-08/07
Address
0x25 (0x45) 0x24 (0x44) 0x23 (0x43) 0x22 (0x42) 0x21 (0x41) 0x20 (0x40) 0x1F (0x3F) 0x1E (0x3E) 0x1D (0x3D) 0x1C (0x3C) 0x1B (0x3B) 0x1A (0x3A) 0x19 (0x39) 0x18 (0x38) 0x17 (0x37) 0x16 (0x36) 0x15 (0x35) 0x14 (0x34) 0x13 (0x33) 0x12 (0x32) 0x11 (0x31) 0x10 (0x30) 0x0F (0x2F) 0x0E (0x2E) 0x0D (0x2D) 0x0C (0x2C) 0x0B (0x2B) 0x0A (0x2A) 0x09 (0x29) 0x08 (0x28) 0x07 (0x27) 0x06 (0x26) 0x05 (0x25) 0x04 (0x24) 0x03 (0x23) 0x02 (0x22) 0x01 (0x21) 0x00 (0x20)
Name
Reserved TCCR0A GTCCR EEARH EEARL EEDR EECR GPIOR0 EIMSK EIFR Reserved Reserved Reserved Reserved TIFR2 TIFR1 TIFR0 PORTG DDRG PING PORTF DDRF PINF PORTE DDRE PINE PORTD DDRD PIND PORTC DDRC PINC PORTB DDRB PINB PORTA DDRA PINA
Bit 7
FOC0A TSM -
Bit 6
WGM00 -
Bit 5
COM0A1 -
Bit 4
COM0A0 -
Bit 3
WGM01 -
Bit 2
CS02 -
Bit 1
CS01 PSR2
Bit 0
CS00 PSR10
Page
95 100/146 21 21 21
EEPROM Address Register High
EEPROM Address Register Low EEPROM Data Register PCIE3 PCIF3 PORTF7 DDF7 PINF7 PORTE7 DDE7 PINE7 PORTD7 DDD7 PIND7 PORTC7 DDC7 PINC7 PORTB7 DDB7 PINB7 PORTA7 DDA7 PINA7 PCIE2 PCIF2 PORTF6 DDF6 PINF6 PORTE6 DDE6 PINE6 PORTD6 DDD6 PIND6 PORTC6 DDC6 PINC6 PORTB6 DDB6 PINB6 PORTA6 DDA6 PINA6 PCIE1 PCIF1 ICF1 PING5 PORTF5 DDF5 PINF5 PORTE5 DDE5 PINE5 PORTD5 DDD5 PIND5 PORTC5 DDC5 PINC5 PORTB5 DDB5 PINB5 PORTA5 DDA5 PINA5 PCIE0 PCIF0 PORTG4 DDG4 PING4 PORTF4 DDF4 PINF4 PORTE4 DDE4 PINE4 PORTD4 DDD4 PIND4 PORTC4 DDC4 PINC4 PORTB4 DDB4 PINB4 PORTA4 DDA4 PINA4 EERIE PORTG3 DDG3 PING3 PORTF3 DDF3 PINF3 PORTE3 DDE3 PINE3 PORTD3 DDD3 PIND3 PORTC3 DDC3 PINC3 PORTB3 DDB3 PINB3 PORTA3 DDA3 PINA3 EEMWE OCF1B PORTG2 DDG2 PING2 PORTF2 DDF2 PINF2 PORTE2 DDE2 PINE2 PORTD2 DDD2 PIND2 PORTC2 DDC2 PINC2 PORTB2 DDB2 PINB2 PORTA2 DDA2 PINA2 EEWE OCF2A OCF1A OCF0A PORTG1 DDG1 PING1 PORTF1 DDF1 PINF1 PORTE1 DDE1 PINE1 PORTD1 DDD1 PIND1 PORTC1 DDC1 PINC1 PORTB1 DDB1 PINB1 PORTA1 DDA1 PINA1 EERE INT0 INTF0 TOV2 TOV1 TOV0 PORTG0 DDG0 PING0 PORTF0 DDF0 PINF0 PORTE0 DDE0 PINE0 PORTD0 DDD0 PIND0 PORTC0 DDC0 PINC0 PORTB0 DDB0 PINB0 PORTA0 DDA0 PINA0 General Purpose I/O Register
21 24 56 56
146 127 98 82 83 83 82 82 82 82 82 82 81 81 82 81 81 81 81 81 81 80 80 80
Note:
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega325/3250/645/6450 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
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7. Instruction Set Summary
Mnemonics
ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER MUL MULS MULSU FMUL FMULS FMULSU RJMP IJMP JMP RCALL ICALL CALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k
Operands
Rd, Rr Rd, Rr Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr k Add two Registers
Description
Rd Rd + Rr
Operation
Flags
Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None Z,C Z,C Z,C Z,C Z,C Z,C None None None None None None None I None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None
#Clocks
1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 3 3 3 4 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2
ARITHMETIC AND LOGIC INSTRUCTIONS Add with Carry two Registers Add Immediate to Word Subtract two Registers Subtract Constant from Register Subtract with Carry two Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers One's Complement Two's Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Multiply Unsigned Multiply Signed Multiply Signed with Unsigned Fractional Multiply Unsigned Fractional Multiply Signed Fractional Multiply Signed with Unsigned Relative Jump Indirect Jump to (Z) Direct Jump Relative Subroutine Call Indirect Call to (Z) Direct Subroutine Call Subroutine Return Interrupt Return Compare, Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less Than Zero, Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set Rd Rd + Rr + C Rdh:Rdl Rdh:Rdl + K Rd Rd - Rr Rd Rd - K Rd Rd - Rr - C Rd Rd - K - C Rdh:Rdl Rdh:Rdl - K Rd Rd * Rr Rd Rd * K Rd Rd v Rr Rd Rd v K Rd Rd Rr Rd 0xFF - Rd Rd 0x00 - Rd Rd Rd v K Rd Rd * (0xFF - K) Rd Rd + 1 Rd Rd - 1 Rd Rd * Rd Rd Rd Rd Rd 0xFF R1:R0 Rd x Rr R1:R0 Rd x Rr R1:R0 Rd x Rr
1 R1:R0 (Rd x Rr) << 1 R1:R0 (Rd x Rr) << 1
PC PC + k + 1 PC Z PC k PC PC + k + 1 PC Z PC k PC STACK PC STACK if (Rd = Rr) PC PC + 2 or 3 Rd - Rr Rd - Rr - C Rd - K if (Rr(b)=0) PC PC + 2 or 3 if (Rr(b)=1) PC PC + 2 or 3 if (P(b)=0) PC PC + 2 or 3 if (P(b)=1) PC PC + 2 or 3 if (SREG(s) = 1) then PCPC+k + 1 if (SREG(s) = 0) then PCPC+k + 1 if (Z = 1) then PC PC + k + 1 if (Z = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (N = 1) then PC PC + k + 1 if (N = 0) then PC PC + k + 1 if (N V= 0) then PC PC + k + 1 if (N V= 1) then PC PC + k + 1 if (H = 1) then PC PC + k + 1 if (H = 0) then PC PC + k + 1 if (T = 1) then PC PC + k + 1
R1:R0 (Rd x Rr) <<
BRANCH INSTRUCTIONS
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Mnemonics
BRTC BRVS BRVC BRIE BRID SBI CBI LSL LSR ROL ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH k k k k k
Operands
Description
Branch if T Flag Cleared Branch if Overflow Flag is Set Branch if Overflow Flag is Cleared Branch if Interrupt Enabled Branch if Interrupt Disabled Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left Through Carry Rotate Right Through Carry Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear Bit Store from Register to T Bit load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Twos Complement Overflow. Clear Twos Complement Overflow Set T in SREG Clear T in SREG Set Half Carry Flag in SREG Clear Half Carry Flag in SREG
Operation
if (T = 0) then PC PC + k + 1 if (V = 1) then PC PC + k + 1 if (V = 0) then PC PC + k + 1 if ( I = 1) then PC PC + k + 1 if ( I = 0) then PC PC + k + 1 I/O(P,b) 1 I/O(P,b) 0 Rd(n+1) Rd(n), Rd(0) 0 Rd(n) Rd(n+1), Rd(7) 0 Rd(0)C,Rd(n+1) Rd(n),CRd(7) Rd(7)C,Rd(n) Rd(n+1),CRd(0) Rd(n) Rd(n+1), n=0..6 Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) SREG(s) 1 SREG(s) 0 T Rr(b) Rd(b) T C1 C0 N1 N0 Z1 Z0 I1 I0 S1 S0 V1 V0 T1 T0 H1 H0 Rd Rr Rd+1:Rd Rr+1:Rr Rd K Rd (X) Rd (X), X X + 1 X X - 1, Rd (X) Rd (Y) Rd (Y), Y Y + 1 Y Y - 1, Rd (Y) Rd (Y + q) Rd (Z) Rd (Z), Z Z+1 Z Z - 1, Rd (Z) Rd (Z + q) Rd (k) (X) Rr (X) Rr, X X + 1 X X - 1, (X) Rr (Y) Rr (Y) Rr, Y Y + 1 Y Y - 1, (Y) Rr (Y + q) Rr (Z) Rr (Z) Rr, Z Z + 1 Z Z - 1, (Z) Rr (Z + q) Rr (k) Rr R0 (Z) Rd (Z) Rd (Z), Z Z+1 (Z) R1:R0
Flags
None None None None None None None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H H None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None
#Clocks
1/2 1/2 1/2 1/2 1/2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 -
BIT AND BIT-TEST INSTRUCTIONS P,b P,b Rd Rd Rd Rd Rd Rd s s Rr, b Rd, b
DATA TRANSFER INSTRUCTIONS MOV MOVW LDI LD LD LD LD LD LD LDD LD LD LD LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM LPM LPM SPM Rd, Z Rd, Z+ Rd, Rr Rd, Rr Rd, K Rd, X Rd, X+ Rd, - X Rd, Y Rd, Y+ Rd, - Y Rd,Y+q Rd, Z Rd, Z+ Rd, -Z Rd, Z+q Rd, k X, Rr X+, Rr - X, Rr Y, Rr Y+, Rr - Y, Rr Y+q,Rr Z, Rr Z+, Rr -Z, Rr Z+q,Rr k, Rr Move Between Registers Copy Register Word Load Immediate Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Direct to SRAM Load Program Memory Load Program Memory Load Program Memory and Post-Inc Store Program Memory
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Mnemonics
IN OUT PUSH POP NOP SLEEP WDR BREAK
Operands
Rd, P P, Rr Rr Rd In Port Out Port Push Register on Stack
Description
Rd P P Rr STACK Rr Rd STACK
Operation
Flags
None None None None None
#Clocks
1 1 2 2 1 1 1 N/A
Pop Register from Stack No Operation Sleep Watchdog Reset Break
MCU CONTROL INSTRUCTIONS (see specific descr. for Sleep function) (see specific descr. for WDR/timer) For On-chip Debug Only None None None
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8. Ordering Information
8.1 ATmega325
Power Supply Ordering Code ATmega325V-8AI ATmega325V-8AU(2) ATmega325V-8MI ATmega325V-8MU(2) ATmega325-16AI ATmega325-16AU(2) ATmega325-16MI ATmega325-16MU(2) Package Type(1) 64A 64A 64M1 64M1 64A 64A 64M1 64M1 Operational Range Industrial (-40C to 85C) Speed (MHz)(3)
8
1.8 - 5.5V
16
2.7 - 5.5V
Industrial (-40C to 85C)
Notes:
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed Grades see Figure 28-1 on page 298 and Figure 28-2 on page 298.
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Package Type 64A 64M1 100A 64-lead, 14 x 14 x 1.0 mm, Thin Profile Plastic Quad Flat Package (TQFP) 64-pad, 9 x 9 x 1.0 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 100-lead, 14 x 14 x 1.0 mm, 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
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8.2
ATmega3250
Power Supply 1.8 - 5.5V 2.7 - 5.5V Ordering Code ATMEGA3250V-8AI ATmega3250V-8AU(2) ATmega3250-16AI ATmega3250-16AU(2) Package Type(1) 100A 100A 100A 100A Operational Range Industrial (-40C to 85C) Industrial (-40C to 85C) 8 16
Speed (MHz)(3)
Notes:
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed Grades see Figure 28-1 on page 298 and Figure 28-2 on page 298.
Package Type 64A 64M1 100A 64-lead, 14 x 14 x 1.0 mm, Thin Profile Plastic Quad Flat Package (TQFP) 64-pad, 9 x 9 x 1.0 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 100-lead, 14 x 14 x 1.0 mm, 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
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8.3 ATmega645
Power Supply Ordering Code ATmega645V-8AI ATmega645V-8AU(2) ATmega645V-8MI ATmega645V-8MU(2) ATmega645-16AI ATmega645-16AU(2) ATmega645-16MI ATmega645-16MU(2) Package Type(1) 64A 64A 64M1 64M1 64A 64A 64M1 64M1 Operational Range Industrial (-40C to 85C)
Speed (MHz)(3)
8
1.8 - 5.5V
16
2.7 - 5.5V
Industrial (-40C to 85C)
Notes:
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed Grades see Figure 28-1 on page 298 and Figure 28-2 on page 298.
Package Type 64A 64M1 100A 64-lead, 14 x 14 x 1.0 mm, Thin Profile Plastic Quad Flat Package (TQFP) 64-pad, 9 x 9 x 1.0 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 100-lead, 14 x 14 x 1.0 mm, 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
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8.4
ATmega6450
Power Supply 1.8 - 5.5V 2.7 - 5.5V Ordering Code ATmega6450V-8AI ATmega6450V-8AU(2) ATmega6450-16AI ATmega6450-16AU(2) Package Type(1) 100A 100A 100A 100A Operational Range Industrial (-40C to 85C) Industrial (-40C to 85C) 8 16
Speed (MHz)(3)
Notes:
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed Grades see Figure 28-1 on page 298 and Figure 28-2 on page 298.
Package Type 64A 64M1 100A 64-lead, 14 x 14 x 1.0 mm, Thin Profile Plastic Quad Flat Package (TQFP) 64-pad, 9 x 9 x 1.0 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 100-lead, 14 x 14 x 1.0 mm, 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
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9. Packaging Information
9.1 64A
PIN 1 B
PIN 1 IDENTIFIER
e
E1
E
D1 D C
0~7 A1 L
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E MIN - 0.05 0.95 15.75 13.90 15.75 13.90 0.30 0.09 0.45 NOM - - 1.00 16.00 14.00 16.00 14.00 - - - 0.80 TYP MAX 1.20 0.15 1.05 16.25 14.10 16.25 14.10 0.45 0.20 0.75 Note 2 Note 2 NOTE
A2
A
Notes: 1.This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum.
E1 B C L e
10/5/2001 2325 Orchard Parkway San Jose, CA 95131 TITLE 64A, 64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO. 64A REV. B
R
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9.2
64M1
D
Marked Pin# 1 ID
E
C
TOP VIEW
SEATING PLANE
A1 A
K L D2
Pin #1 Corner
0.08 C
SIDE VIEW
1 2 3
Option A
Pin #1 Triangle
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL
Option B
Pin #1 Chamfer (C 0.30)
E2
MIN 0.80 - 0.18 8.90 5.20 8.90 5.20
NOM 0.90 0.02 0.25 9.00 5.40 9.00 5.40 0.50 BSC
MAX 1.00 0.05 0.30 9.10 5.60 9.10 5.60
NOTE
A A1 b D
K b e
Option C
D2
Pin #1 Notch (0.20 R)
E E2 e L
BOTTOM VIEW
0.35 1.25
0.40 1.40
0.45 1.55
Note: 1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD. 2. Dimension and tolerance conform to ASMEY14.5M-1994.
K
5/25/06 2325 Orchard Parkway San Jose, CA 95131 TITLE 64M1, 64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm, 5.40 mm Exposed Pad, Micro Lead Frame Package (MLF) DRAWING NO. 64M1 REV. G
R
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9.3 100A
PIN 1 B
PIN 1 IDENTIFIER
e
E1
E
D1 D C
0~7 A1 L
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E MIN - 0.05 0.95 15.75 13.90 15.75 13.90 0.17 0.09 0.45 NOM - - 1.00 16.00 14.00 16.00 14.00 - - - 0.50 TYP MAX 1.20 0.15 1.05 16.25 14.10 16.25 14.10 0.27 0.20 0.75 Note 2 Note 2 NOTE
A2
A
Notes:
1. This package conforms to JEDEC reference MS-026, Variation AED. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.08 mm maximum.
E1 B C L e
10/5/2001 2325 Orchard Parkway San Jose, CA 95131 TITLE 100A, 100-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness, 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO. 100A REV. C
R
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10. Errata
10.1 Errata ATmega325
The revision letter in this section refers to the revision of the ATmega325 device. 10.1.1 ATmega325 Rev. C * Interrupts may be lost when writing the timer registers in the asynchronous timer 1. Interrupts may be lost when writing the timer registers in the asynchronous timer If one of the timer registers which is synchronized to the asynchronous timer2 clock is written in the cycle before a overflow interrupt occurs, the interrupt may be lost. Problem Fix/ Workaround Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2. 10.1.2 ATmega325 Rev. B Not sampled. 10.1.3 ATmega325 Rev. A * Interrupts may be lost when writing the timer registers in the asynchronous timer 1. Interrupts may be lost when writing the timer registers in the asynchronous timer If one of the timer registers which is synchronized to the asynchronous timer2 clock is written in the cycle before a overflow interrupt occurs, the interrupt may be lost. Problem Fix/ Workaround Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2.
10.2
Errata ATmega3250
The revision letter in this section refers to the revision of the ATmega3250 device.
10.2.1
ATmega3250 Rev. C * Interrupts may be lost when writing the timer registers in the asynchronous timer 1. Interrupts may be lost when writing the timer registers in the asynchronous timer If one of the timer registers which is synchronized to the asynchronous timer2 clock is written in the cycle before a overflow interrupt occurs, the interrupt may be lost. Problem Fix/ Workaround Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2.
10.2.2
ATmega3250 Rev. B Not sampled.
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10.2.3 ATmega3250 Rev. A * Interrupts may be lost when writing the timer registers in the asynchronous timer 1. Interrupts may be lost when writing the timer registers in the asynchronous timer If one of the timer registers which is synchronized to the asynchronous timer2 clock is written in the cycle before a overflow interrupt occurs, the interrupt may be lost. Problem Fix/ Workaround Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2.
10.3
Errata ATmega645
The revision letter in this section refers to the revision of the ATmega645 device.
10.3.1
ATmega645 Rev. A * Interrupts may be lost when writing the timer registers in the asynchronous timer 1. Interrupts may be lost when writing the timer registers in the asynchronous timer If one of the timer registers which is synchronized to the asynchronous timer2 clock is written in the cycle before a overflow interrupt occurs, the interrupt may be lost. Problem Fix/ Workaround Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2.
10.4
Errata ATmega6450
The revision letter in this section refers to the revision of the ATmega6450 device.
10.4.1
ATmega6450 Rev. A * Interrupts may be lost when writing the timer registers in the asynchronous timer 1. Interrupts may be lost when writing the timer registers in the asynchronous timer If one of the timer registers which is synchronized to the asynchronous timer2 clock is written in the cycle before a overflow interrupt occurs, the interrupt may be lost. Problem Fix/ Workaround Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2.
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2570LS-AVR-08/07
11. Datasheet Revision History
Please note that the referring page numbers in this section are referring to this document. The referring revision in this section are referring to the document revision.
11.1
Rev. 2570L - 08/07
1. 2. 3. 4. 5. 6. Updated "Features" on page 1. Added "Data Retention" on page 8. Updated "Serial Programming Algorithm" on page 280. Updated "Speed Grades" on page 298. Updated "System and Reset Characteristics" on page 300. Updated the Register Description at the end of each chapter.
11.2
Rev. 2570K - 04/07
1. Updated "Errata" on page 24.
11.3
Rev. 2570J - 11/06
1. 2. Updated Table 28-7 on page 303. Updated note in Table 28-7 on page 303.
11.4
Rev. 2570I - 07/06
1. 2. Updated Table 15-6 on page 91. Updated Table 15-2 on page 96, Table 15-4 on page 96, Table 17-3 on page 123, Table 17-5 on page 124, Table 18-2 on page 142 and Table 18-4 on page 143. Updated "Fast PWM Mode" on page 114. Updated Features in "USI - Universal Serial Interface" on page 184. Added "Clock speed considerations." on page 190. Updated "Errata" on page 24.
3. 4. 5. 6.
11.5
Rev. 2570H - 06/06
1. 2. 3. Updated "Calibrated Internal RC Oscillator" on page 28. Updated "OSCCAL - Oscillator Calibration Register" on page 31. Added Table 28-2 on page 299.
26
ATmega325/3250/645/6450
2570LS-AVR-08/07
ATmega325/3250/645/6450
11.6 Rev. 2570G - 04/06
1. Updated "Calibrated Internal RC Oscillator" on page 28.
11.7
Rev. 2570F - 03/06
1. Updated "Errata" on page 24.
11.8
Rev. 2570E - 03/06
1. 2. 3. 4. 5. 6. 7. 8. 9. 10 11. 12. 13. Added Addresses in Register Descriptions. Updated number of Genearl Purpose I/O pins. Correction of Bitnames in "Register Summary" on page 9. Added "Resources" on page 8. Updated "Power Management and Sleep Modes" on page 34. Updated "Bit 0 - IVCE: Interrupt Vector Change Enable" on page 53. Updated Introduction in "I/O-Ports" on page 59. Updated 19."SPI - Serial Peripheral Interface" on page 147. Updated "Bit 6 - ACBG: Analog Comparator Bandgap Select" on page 198. Updated Features in "Analog to Digital Converter" on page 200. Updated "Prescaling and Conversion Timing" on page 203. Updated "ATmega325/3250/645/6450 Boot Loader Parameters" on page 261. Updated "DC Characteristics" on page 296.
11.9
Rev. 2570D - 05/05
1. 2. 3. 4. 5. 6. 7. 8. 9. MLF-package alternative changed to "Quad Flat No-Lead/Micro Lead Frame Package QFN/MLF". Added "Pin Change Interrupt Timing" on page 54. Updated "Signature Bytes" on page 267. Updated Table 27-15 on page 281. Added Figure 27-12 on page 283. Updated Figure 23-9 on page 208 and Figure 27-5 on page 275. Updated algorithm "Enter Programming Mode" on page 270. Added "Supply Current of I/O modules" on page 310. Updated "Ordering Information" on page 16.
11.10 Rev. 2570C - 11/04
1. 2. 3. "0 - 8 MHz @ 2.7 - 5.5V, 0 - 16 MHz @ 4.5 - 5.5V" on page 1 updated. Table 9-8 on page 29 updated. COM01:0 renamed COM0A1:0 in "8-bit Timer/Counter0 with PWM" on page 84.
27
2570LS-AVR-08/07
4. 5. 6. 7. 8.
PRR-bit descripton added to "16-bit Timer/Counter1" on page 101, "SPI - Serial Peripheral Interface" on page 147, and "USART0" on page 156. "Part Number" on page 224 updated. "Typical Characteristics" on page 305 updated. "DC Characteristics" on page 296 updated. "Alternate Functions of Port G" on page 75 updated.
11.11 Rev. 2570B - 09/04
1. Updated "Ordering Information" on page 16.
11.12 Rev. 2570A - 09/04
1. Initial revision.
28
ATmega325/3250/645/6450
2570LS-AVR-08/07
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2570LS-AVR-08/07

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